1. Technical Field
The present invention relates in general to testing of bus fault isolation and recovery mechanisms and in particular to design verification of bus fault isolation and recovery mechanisms. Still more particularly, the present invention relates to error injection for design verification of bus fault isolation and recovery mechanisms.
2. Description of the Related Art
All data processing systems include busses, employed to transfer data to and from processors, memory controllers, memory, and input/output (I/O) devices. For various reasons, these busses are susceptible to errors such as electrical noises, imperfect connection, and the like. Various bus architectures provide for error detection and recovery in the event of such errors. As a result, error checking and recovery handling is typically built into the design of data processing system busses, generally in the form of address and data bus parity checking and error correction code (ECC) checking.
Error checking and handling recovery system designs must themselves be verified to ensure proper operation. Therefore, to ensure that error detection, capture, reporting, and correction facilities within fault isolation or recovery designs work as intended, design verification methodologies and tools are required which simulate errors likely to occur on a data processing system bus. The simulated errors should mimic the actual hardware errors which occur while the system is running typical software applications, and should work properly on all bus transactions supported by the bus architecture for which the error checking and recovery system being tested is designed.
Existing bus design verification tools are generally designed for the verification of bus functions for a given architecture, not particularly for verifying error detection and recovery mechanisms for a given design. Therefore such verification tools are prohibitively expensive and complex. Moreover, such verification tools are typically designed for one specific bus architecture, so that the fault isolation and recovery verification methodologies and tools are not applicable to other bus architectures. Finally, available tools are not capable of causing a single cycle, precise error.
It would be desirable, therefore, to provide a design verification mechanism for error detection and recovery facilities which is inexpensive, easy to assemble using off-the-shelf components, and very simple to use. It would further be advantageous for the methodology and tool utilized for design verification to be readily applicable to multiple bus architectures.